The present invention relates to a method for fabricating a trench capacitor.
Capacitors are generally used to store charge in integrated circuits (ICs). Thus, the dynamic random access memories (DRAMs) of memory ICs are in each case composed of a selection transistor and a storage capacitor. The information is stored in the storage capacitor in the form of electrical charges. A memory IC includes a matrix of such DRAM cells connected up in the form of rows and columns. Usually, the row connections are referred to as word lines and the column connections as bit lines. In this case, the selection transistor and the storage capacitor in the DRAM cell are connected to one another in such a way that when the selection transistor is driven via a word line, the charge of the storage capacitor can be read in and out via a bit line.
A priority in the technological development of memory ICs with DRAMs is the storage capacitor. In order to obtain an adequate read signal from this storage capacitor, the storage capacitance must be approximately 25-40 fF. In order to provide for such a storage capacitance given that the cell area continually decreases from technological step to technological step for the DRAMs, storage capacitors have been developed, therefore, which utilize the third dimension. In DRAM cells such three-dimensional storage capacitors are embodied for example as trench capacitors which are fabricated by etching a trench into the semiconductor substrate, and filling the trench with a dielectric layer and a first storage electrode. The semiconductor substrate serves as a second storage electrode. The selection transistor of the DRAM cells is then usually formed on the planar semiconductor surface beside the trench capacitor.
The miniaturization of the DRAM cells continues to advance, even with the trench capacitors. Accordingly, ways of ensuring a uniform capacitor capacitance are being sought due to reducing the cell area by decreasing the trench diameter. One possibility here is to increase the depth of the trenches, but this procedure has in the meantime come up against both technological and economic limits. On one hand, the production of ever deeper trenches with a simultaneously reduced trench diameter requires etching methods which achieve very high aspect ratios (ratio of column depth to column width). In the case of the aspect ratio, however, limits are set on the known etching methods. Moreover, above a specific depth, the trench etching requires a greatly prolonged etching time, which significantly increases the costs of the etching process.
Therefore, as an alternative and in addition to further deepening of the trenches, methods are increasing being used which allow the surface within the trench capacitor to be enlarged in order thereby to provide for an adequate storage capacitance. Thus, methods are known in which the trench capacitor is widened in its lower region by means of an additional etching step, as a result of which the capacitor area can be increased. However, the etching processes required for such widening of the trenches likewise come up against technological limits.
In addition to the trench capacitors stacked capacitors are also used for three-dimensional formation of storage capacitors in memory ICs. In principle, a stacked capacitor includes two conductive layers which are arranged one above the other and are isolated by a dielectric layer. In DRAM cells, stacked capacitors are generally formed above the planar selection transistors, and one of the two capacitor electrodes is electrically connected to the selection transistor. In order to achieve the largest possible capacitor area in such stacked capacitors and thus to provide for an adequate storage capacitance, the dielectric layer between the two conductive capacitor layers is preferably embodied in a folded manner. Such stacked capacitors are known under the designation crown stacked capacitors.
Furthermore, in the case of stacked capacitors, methods are also used in which the surface of the conductive capacitor layers is roughened and thereby enlarged. In particular, for the purpose of enlarging the surface, rough polysilicon, so-called hemispherical grain silicon HSG, is used, in the case of which silicon grains having a size of approximately 10 to 100 nm are produced with the aid of a special deposition technique or a temperature treatment. However, since in technological terms the HSG process can be controlled only with very great difficulty, this method for enlarging the surface of the capacitor electrodes and thus for increasing the total capacitance of the capacitor has hitherto been used exclusively with stacked capacitors. Methods for fabricating HSG layers in stacked capacitors are disclosed inter alia in U.S. Pat. Nos. 5,723,379, 5,858,852 and 5,858,837.
Furthermore, U.S. Pat. No. 5,877,061 discloses a trench capacitor in which an improved capacitor capacitance is achieved by means of a roughened surface in the region of the capacitor electrodes. For this purpose, a granular polysilicon layer or an HSG silicon layer is deposited in the region in which the capacitor electrodes are intended to be formed in the trench, and is subsequently etched away isotropically, so that a roughened silicon surface remains in the capacitor electrode region. This technique for increasing the capacitance in the trench capacitor is complicated, however, since additional etching processes are provided. Furthermore, there is the risk that the granular polysilicon layer or the HSG silicon layer will not be completely etched away in particular in the collar region, which serves to insulate the capacitor electrodes, as a result of which leakage current paths can arise.
In the case of low or even a lack of etching selectivity with respect to the etching mask, isotropic etchings furthermore tend to compensate roughnesses that are originally present, as a result of which the roughness initially present in the HSG can only be incompletely transferred to the underlying silicon.
It would also be desirable, however, if it were possible in the case of trench capacitors to obtain enlarged capacitor surfaces, and thus an increased storage capacitance, by means of rough surfaces according to the HSG method. A use of HSG silicon in trench capacitors has not succeeded, however, in particular because the known methods do not allow the HSG silicon to be limited to the regions in the trench capacitor which serve as an electrode surface. In trench capacitors, a dielectric collar is usually produced in the region of the trench in order to prevent a parasitic vertical field-effect transistor from being produced. When using HSG silicon for enlarging the electrode surface, there is the risk, however, that, in particular, HSG silicon will also remain in the collar region, which can then lead to undesirable leakage currents.
Published European Patent Application EP 980 100 A2 discloses a method of the generic type. In this known method for fabricating a trench capacitor, an HSG silicon layer is first produced on the entire surface of the trench. Afterward, the lower region of the HSG silicon layer is masked and the HSG silicon layer in the upper region is then converted into an oxide layer. A lower part of this oxide layer is then extended and used as an insulation collar.
It is accordingly an object of the invention to provide a simple and reliable method for producing an HSG silicon layer in a trench capacitor which overcomes the above-mentioned disadvantageous of the prior art methods of this general type. In particular, it is an object of the invention to provide such a method in which the HSG silicon layer is limited exclusively to the region of the electrode surfaces.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating a trench capacitor, that includes steps of: providing a silicon substrate; forming a trench, having a lower region and a surface, in the silicon substrate; and forming a doped layer in the silicon substrate in the lower region of the trench. In addition, a roughened silicon layer that has silicon grains with a diameter ranging from essentially 10 to 100 nm is produced in the lower region of the trench by performing steps of: depositing an amorphous silicon layer on all of the surface of the trench, patterning the amorphous silicon layer by etching such that the amorphous silicon layer is limited to the lower region of the trench, and subsequently nucleating the amorphous silicon layer to form the silicon grains. A dielectric intermediate layer is applied on the roughened silicon layer; and the trench is filled with a doped layer.
In accordance with an added feature of the invention, the step of producing the roughened silicon layer is performed by: depositing essentially smooth amorphous silicon at a temperature below the transition temperature from amorphous silicon to polycrystalline silicon; and subsequently converting the essentially smooth silicon layer into the roughened silicon layer by performing a heating step at a temperature selected from the group consisting of a temperature close to the transition temperature and a temperature above the transition temperature.
In accordance with an additional feature of the invention, before producing the roughened silicon layer, an insulation layer is formed in an upper region of the trench.
In accordance with another feature of the invention, the nucleating step is performed by selectively nucleating the amorphous silicon layer in the lower region of the trench to form the silicon grains.
In accordance with a further added feature of the invention, after producing the roughened silicon layer, an insulation layer is formed in an upper region of the trench.
In this embodiment, selective production of a roughened silicon layer in the lower trench region is performed. Amorphous, non-roughened silicon is deposited on the trench surface and then is patterned, as a result of which the amorphous silicon layer, from which the silicon grains are subsequently produced, remains only in the lower trench region in which the capacitor electrodes are formed. This configuration makes it possible, in a particularly simple manner, to produce the roughened silicon layer only in the region of the electrode surfaces.
With the foregoing and other objects in view there is also provided, in accordance with the invention, a method for fabricating a trench capacitor, that includes steps of: providing a silicon substrate; forming a trench, which has a lower region and a surface, in the silicon substrate; and forming a doped layer in the silicon substrate in the lower region of the trench. A roughened silicon layer, having silicon grains with a diameter ranging from essentially 10 to 100 nm, is produced in the lower region of the trench by: producing the roughened silicon layer on all of the surface of the trench, masking the lower region of the trench, and using an etching method to remove the roughened silicon layer from an upper region of the trench. A dielectric intermediate layer is applied on the roughened silicon layer, and the trench is filled with a doped layer.
In accordance with an added feature of this embodiment of the invention, before performing the etching method to remove the roughened silicon layer, the roughened silicon layer is planarized in the upper region of the trench.
In accordance with an additional feature of this embodiment of the invention, the planarizing step is performed using a high-temperature step in which the roughened silicon layer in the lower region of the trench is masked by a temperature-stable layer.
In accordance with another feature of this embodiment of the invention, the step of producing the roughened silicon layer is performed by depositing silicon at a transition temperature between amorphous silicon and polycrystalline silicon.
In accordance with a further feature of this embodiment of the invention, the step of producing the roughened silicon layer is performed by: depositing an essentially smooth amorphous silicon at a temperature below a transition temperature between amorphous silicon and polycrystalline silicon; and subsequently converting the essentially smooth silicon layer into the roughened silicon layer by performing a heating step at a temperature selected from the group consisting of a temperature close to the transition temperature and a temperature above the transition temperature.
In accordance with a further added feature of this embodiment of the invention, before producing the roughened silicon layer, an insulation layer is formed in an upper region of the trench.
In accordance with a further additional feature of this embodiment of the invention, the nucleating step is performed by selectively nucleating the amorphous silicon layer in the lower region of the trench to form the silicon grains.
In accordance with yet an added feature of this embodiment of the invention, after producing the roughened silicon layer, an insulation layer is formed in an upper region of the trench.
In other words in this embodiment, a roughened silicon layer is first produced on the entire surface of the trench. The lower region of this roughened silicon layer is subsequently masked and the roughened silicon layer in the upper region then is removed using an etching method. In order to remove the roughened silicon layer in the upper trench region, it is preferable to first planarize the previously produced silicon grains under suitable process conditions. The roughened silicon layer in the lower trench region is preferably protected by a temperature-stable layer during the planarization.
The process sequence ensures that the roughened silicon layer is reliably removed in the insulation collar region and the masking in the lower region simultaneously prevents this roughened silicon layer region from being damaged during the patterning. In this case, the planarization step that is additionally possible enables particularly simple removal or alteration of the roughened silicon layer in the upper trench region.
Using the method, it is thus possible to produce a trench capacitor in which the surface of the capacitor electrodes is greatly enlarged by the roughened silicon surface, as a result of which the capacitance of the trench capacitor is increased and it is simultaneously ensured that the roughened silicon layer is formed only on the electrode surface within the trench. This construction ensures that no leakage current flows between the electrodes of the trench capacitor, which leakage current would lead to a rapid loss of the stored charge in the trench capacitor. At the same time, limiting the roughened silicon layer to the electrode surface prevents the occurrence of impermissible constriction of the upper trench section, which is necessary for making contact with the selection transistor.
In order to fabricate a trench capacitor, after the formation of a doped layer in the silicon substrate in the lower region of the trench, either an insulation layer is produced in the upper region of the trench for the purpose of forming the insulation collar and the roughened silicon layer is then produced in the lower region of the trench, or after the formation of the doped layer in the silicon substrate in the lower region of the trench, first the roughened silicon layer is produced in this region and then the insulation layer for the insulation collar is formed in the upper region.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a trench capacitor and method for fabricating it, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.